Sara Royuela (on behalf of Eduardo Quiñones), "Ampere- A model-driven development framework for highly parallel and energy-efficient computation supporting multi-criteria optimization", HiPEAC 2023, European Network on High-performance Embedded Architecture and Compilation 16-18 January, Toulous, France.
Mazzola, S., Benz, T., Forsberg, B., Benini, L. (2022). A Data-Driven Approach to Lightweight DVFS-Aware Counter-Based Power Modeling for Heterogeneous Platforms. In: Orailoglu, A., Reichenbach, M., Jung, M. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2022. Lecture Notes in Computer Science, vol 13511. Springer, Cham. https://doi.org/10.1007/978-3-031-15074-6_22
Yu, Chenle, Sara Royuela, and Eduardo Quiñones. "A Low Overhead Tasking Model for OpenMP." In European Conference on Parallel Processing, pp. 520-524. Springer, Cham, 2022.
M. Samadi Gharajeh, S. Royuela, L. Miguel Pinho, T. Carvalho and E. Quiñones, "Heuristic-based Task-to-Thread Mapping in Multi-Core Processors," 2022 IEEE 27th International Conference on Emerging Technologies and Factory Automation (ETFA), 2022, pp. 1-4, doi: 10.1109/ETFA52439.2022.9921453.
A. Saeed, D. Dasari, D. Ziegenbein, V. Rajasekaran, F. Rehm, M. Pressler, A. Hamann, D. Mueller-Gritschneder, A. Gerstlauer, and U. Schlictmann,"Memory Utilization-Based Dynamic Bandwidth Regulation for Temporal Isolation in Multi-Cores," 2022 IEEE 28th Real-Time and Embedded Technology and Applications Symposium (RTAS), 2022, pp. 133-145, doi: 10.1109/RTAS54340.2022.00019.
Casini, D., Pazzaglia, P., Biondi, A., & Natale, M.D. (2022). Optimized partitioning and priority assignment of real-time applications on heterogeneous platforms with hardware acceleration. J. Syst. Archit., 124, 102416.
Submitted and accepted
A. Stevanato, T. Cucinotta, L. Abeni, D. B. de Oliveira. "An Evaluation of Adaptive Partitioning of Real-Time Workloads on Linux," (to appear) in Proceedings of the 24th IEEE International Symposium on Real-Time Distributed Computing (IEEE ISORC 2021), June 1-3, 2021, Daegu, South Korea.
Presentation at the IEEE ISORC 2021 international conference
Biruk Seyoum, Alessandro Biondi, Marco Pagani, Giorgio Buttazzo. Automating the design flow under dynamic partial reconfiguration for hardware-software co-design in FPGA SoC.
Luis Miguel Pinho. Challenges in Resource Management in the ELASTIC and AMPERE European Projects.